Threshold network synthesis and opti- mization and its application to nanotechnologies.
We propose an algorithm for efficient threshold network synthesis of arbitrary multi-output Boolean functions. Many nanotechnologies, such as resonant tunneling diodes (RTDs), quantum cellular automata (QCA), and single electron tunneling (SET), are capable of implementing threshold logic efficiently. The main purpose of this work is to bridge the current wide gap between research on nanoscale devices and research on synthesis methodologies for generating optimized networks utilizing these devices. While functionally-correct threshold gates and circuits based on nanotechnologies have been successfully demonstrated, there exists no methodology or design automation tool for general multi-level threshold network synthesis. We have built the first such tool, ThrEshold Logic Synthesizer (TELS), on top of an existing Boolean logic synthesis tool. Experiments with 56 multioutput benchmarks indicate that, compared to traditional logic synthesis, upto 80.0% and 70.6% reduction in gate count and interconnect count, respectively, is possible with the average being 22.7% and 12.6%, respectively. Furthermore, the synthesized networks are well-balanced structurally. The novelty of this work lies in the introduction of the first comprehensive synthesis methodology and tool for general multi-level threshold logic design.
|Main Author:||Rui Zhang.|
|Other Authors:||Gupta, Pallav., Zhong, Lin., Jha, Niraj K.|