A high-level interconnect power model for design space exploration.
In this paper, we present a high-level power model to estimate the power consumption in semi-global and global interconnects. Such interconnects are used for communications between logic modules, clock distribution networks, and power supply rails. The main purpose of our model is to set forward a simple methodology to efficiently obtain first-order estimates of interconnect power in early stages of the design process. Hence, the objective is to provide designers and/or high-level design automation tools with a way to quickly explore the design space and weed out architectures whose interconnect power requirements do not meet the allocated power budget. In addition to switching power, which includes inter-wire coupling, our model also considers power due to vias and repeaters. Our experimental results show that in comparison to an accurate low-level model, the error in our method in estimating total switching power is only 6% (while the speedup is three-to-four orders of magnitude), and an estimate of the numbers of vias (hence, via power) is within 3% agreement of that obtained for designs synthesized by commercial tools. Furthermore, we develop a probabilistic segment length distribution model for cases in which Rent’s rule is inadequate. By analyzing the netlists of a set of complex designs, we have been able to validate our segment length distribution model. The novelty of this work lies in the introduction of a high-level interconnect modeling methodology in which it is possible to efficiently compute all the major sources of power consumption in interconnects and hence, enable interconnect-aware, high-level design space exploration.
|Main Author:||Gupta, Pallav.|
|Other Authors:||Zhong, Lin., Jha, Niraj K.|